The present invention relates to circuits and methods for optimization of power in integrated circuits (ICs) and particularly in ultra-low-power metal-oxide-semiconductor (MOS) and complementary metal-oxide-semiconductor (CMOS) logic circuits.
ICs designed for ultra-low-power applications require optimization (minimization) of both static and dynamic power dissipation. Static power dissipation is caused by steady-state current leaking. Dynamic power dissipation is caused by additional currents needed when logic circuits switch between low and high states. Reduction of dynamic power dissipation can be achieved by switching circuits no more often than strictly needed. In MOS and CMOS technologies, leakage currents and logic switching speeds are correlated, so reduction of static power dissipation can be achieved by reducing leakage currents to the minimum at which logic gates can switch at their required speed.
CMOS manufacturing processes are popular for digital ICs as they offer relatively low current leakage for general-purpose applications, as will be explained below. Several CMOS process technologies exist, including P-type substrate with N-wells, with deep N-wells, or triple-wells, silicon-on-insulator (SOI), and others. P-type substrate with N-wells is one of the simplest and therefore least expensive ways to make CMOS.
FIG. 1 illustrates examples of transistors used in CMOS ICs. Example 100a provides schematic views of P-type semiconductor MOS (PMOS) transistor 110a and N-type semiconductor MOS (NMOS) transistor 120b. Example 100b provides cross-sections of a silicon implementation of PMOS transistor 110b and NMOS transistor 120b, in a P-type substrate with N-well technology.
A MOS (PMOS or NMOS) transistor, as used in this specification, includes four terminals electrically coupling to: a (metal or semiconductor, such as polysilicon) gate, a (semiconductor) source, a (semiconductor) drain, and a (semiconductor) body. The MOS transistor has a body into which the source and drain are diffused. A MOS transistor may have its individual body, or share a body with other MOS transistors of the same or a similar type. The MOS transistor has a channel for conducting current between its source and drain. The channel is situated in the body under the gate and under an oxide insulator, typically silicon-dioxide. The channel's conductivity can be controlled by a voltage VGS between the gate and source. It is further determined by a static threshold voltage Vt.
PMOS transistor 110a has gate terminal 112a, source terminal 114a, body terminal 116a, and drain terminal 118a. NMOS transistor 120a has gate terminal 122a, drain terminal 124a, body terminal 126a, and source terminal 128a. 
PMOS transistor 110b and NMOS transistor 120b are physically implemented on a wafer that may include P-silicon bulk 102b (e.g., a P-type substrate). PMOS transistor 110b includes, or is included in, a well of N-type silicon (an N-well) 104b diffused into bulk 102b. N-well 104b forms the body of PMOS transistor 110b. PMOS transistor 110b has gate terminal 112b, source terminal 114b, body terminal 116b (this is a terminal to the N-well 104b body), and drain terminal 118b. Source terminal 114b connects to a source of P+ silicon diffused into N-well 104b. Drain terminal 118b connects to a drain of P+ silicon diffused into N-well 104b. Gate terminal 112b connects to a gate of poly-silicon over a silicon-dioxide insulator over a channel in N-well 104b between the source and the drain. Body terminal 116b connects to N-well 104b via N+ silicon diffused into N-well 104b. 
Bulk 102b forms the body of NMOS transistor 120b, which has a gate terminal 122b, drain terminal 124b, body terminal 126b, and source terminal 128b. Drain terminal 124b connects to a drain of N+ silicon diffused into bulk 102b. Source terminal 128b connects to a source of N+ silicon diffused into bulk 102b. Gate terminal 122b connects to a gate of poly-silicon over silicon-dioxide over a channel in bulk 102b between the source and the drain. Body terminal 126b connects to bulk 102b via P+ silicon diffused into bulk 102b. 
In normal operation, N-well 104b may be kept (“biased”), via terminal 116b, at the highest voltage in an integrated system, and bulk 102b may be biased, via terminal 126b, at the lowest voltage in the system. This way, bulk 102b forms zero-biased or reverse-biased diodes with N-well 104b, drain 124b, and source 128b. N-well 104b forms zero-biased or reverse-biased diodes with source 114b and drain 118b. Zero-biased diodes carry no current. Reverse-biased diode may carry a negligibly small leakage current. Therefore, bulk 102b effectively insulates NMOS transistor 120b from any other devices, and N-well 104b effectively insulates PMOS transistor 110b from any other devices.
CMOS logic circuits use both PMOS and NMOS transistors, where gate terminals may be used to input signals, drain terminals to output signals, and source terminals for signal reference. Transistor body terminals are for biasing only, to provide adequate insulation. Most often, CMOS gates include PMOS transistors whose sources couple to the highest available voltage and NMOS transistors whose sources couple to the lowest available voltage. Therefore, in standard CMOS gates, PMOS transistors typically couple their source terminals directly to their body (i.e. N-well) terminal, and NMOS transistors typically couple their source terminals directly to their body (i.e. bulk) terminal.
FIG. 2 illustrates an example 200 of conventional CMOS logic design. CMOS logic design 200 includes inverter 210 and other logic gates 230. Inverter 210 and other logic gates 230 take their energy from power supply (VDD) rail 202, returning used currents to ground (GND) rail 204. Inverter 210 may include a PMOS transistor 216 and an NMOS transistor 220. Inverter 210 has an input 212 coupled with the gates of both MOS transistors 216 and 220. Source terminal 217 and body terminal 218 of transistor 216 are coupled with VDD rail 202, whereas source terminal 221 and body terminal 222 of transistor 220 are coupled with GND rail 204. Inverter 210 has an output 214 coupled with drains of both transistors 216 and 220.
Similar to inverter 210, other logic gates 230 will typically couple their PMOS transistor body terminals to VDD rail 202 and their NMOS transistor body terminals to GND rail 204. CMOS gates, such as inverter 210, are popular because of their relatively low use of energy. For instance, when a high voltage (close to VDD level) is applied to input 212, PMOS transistor 216 will conduct very little, i.e. almost no current flows from VDD rail 202 via its source terminal to its drain terminal. Hence, almost no current flows from NMOS transistor 220's drain via its source to GND rail 204. When a low voltage (close to GND level) is applied to input 210, NMOS transistor 220 will conduct very little, i.e. almost no current flows to GND rail 204 via its source terminal from its drain terminal. Hence, almost no current flows from VDD rail 202 via PMOS transistor 216's source to its drain. Thus, when inverter 210 is in a steady state, very little current flows. The same holds for other logic gates in CMOS, such as NANDs, NORs, etc.
The level of conductance (or insulation) in a MOS transistor's channel depends on a voltage VGS applied between its gate and its source with respect to its threshold voltage Vt, which in turn is dependent on a voltage VSB between the source and the body. When VGS is larger than Vt, a channel conducts maximally, and when VGS is smaller than Vt the channel's conductance is reduced. Many CMOS processes have been developed to operate at low voltages. A CMOS process may offer transistors with one or more threshold voltages: high-Vt transistors offer low leakage, at the expense of speed; low-Vt transistors may offer high speed at the expense of leakage; zero-Vt transistors offer even higher speed at the expense of additional leakage. Zero-Vt transistors may be useful for bypass switches and (analog) source followers.
To allow for simple logic circuits, high-Vt and low-Vt threshold voltages are designed to be useful even when VSB equals zero, i.e. when a MOS transistor source is directly coupled with its body. In those cases, when VGS equals zero, the channel will have a small remaining conductance compared to when VGS is larger than Vt. The remaining conductance will allow a small current to pass the channel, which is a main component of the MOS transistor's leakage current that causes static power dissipation.
When a gate or inverter is switched from a low to a high state or vice versa, its input(s) and output(s) additionally dissipate power dynamically. This is caused by parasitic capacitances cGB between gate and body, and cDB between drain and body, that need to be charged or discharged from a prior state to a new state. Dynamic power dissipation due to charging and discharging parasitic capacitances is proportional to the average frequency of switching the gate or inverter and to the square of the parasitic capacitances' voltage swing, usually practically the supply voltage VDD. Dynamic power dissipation may further be exacerbated if during some part of the switch time both a PMOS and an NMOS transistor are conducting, and a direct path with low conductance exists between the VDD and GND rails.
In many applications, standard logic gates available in standard CMOS processes provide reasonable compromises between speed of switching, dynamic power dissipation due to switching, and static power dissipation due to leakage. However, for some ultra-low-power applications, the compromise and optimization options offered by standard logic gates are not acceptable. For instance, in applications that are dependent on power harvesting, such as passive radio-frequency identification (RFID) tags, or that require a very long battery life, static power dissipation must be reduced to much smaller levels than offered by standard logic cells.
A standard way to reduce power dissipation in an IC it to implement clock gating. Temporarily unused blocks of logic receive no clock pulses, and are therefore in a steady state. Although this reduces dynamic power dissipation, it does not address static power dissipation. Further standard solutions include using high-Vt logic gates for slowly switching signals and low-Vt logic gates for fast switching signals. This somewhat reduces static power dissipation, but not by much.
A further conventional solution to also reduce static power dissipation is to implement power gating for logic blocks that are temporarily not in use. In power gating, one or more switches interrupt all power to those blocks. However, a disadvantage of this solution is that the switch(es) may cost a lot of area to maintain low noise levels in the supplied power. Another disadvantage is that circuits that are in use may still suffer from high static power dissipation. Yet another conventional solution is to use body biasing—biasing a device's body at a different voltage than its embedded source.
FIGS. 3A-B illustrate conventional examples 300 of reverse body biasing for reducing leakage current and 350 of forward body biasing for increasing speed. Example 300 in FIG. 3A includes inverter 320 and other logic gates 330. Supply voltage source 310 coupled to GND rail 304 provides a supply voltage for VDD rail 302. First body-bias voltage source 312 supplies first body-bias voltage VBP for N-well body-bias rail 306, and second body-bias voltage source 314 supplies second body-bias voltage VBN for bulk body-bias rail 308. Inverter 320 includes PMOS transistor 322 with a source 323 coupled to VDD rail 302 and body terminal 324 coupled to N-well body-bias rail 306. It further includes NMOS transistor 326 with a source 327 coupled to GND rail 304 and body terminal 328 coupled to bulk body-bias rail 308. Similarly, other logic gates 330 include PMOS transistors with sources coupled to VDD rail 302 and body terminals coupled to N-well body-bias rail 306, and NMOS transistors with sources coupled to GND rail 304 and body terminals coupled to bulk body-bias rail 308. First body-bias voltage VBP is higher than VDD, and second body-bias voltage VBN is lower than GND. As a result of higher source-to-bulk voltage VBS for PMOS transistor 322 and NMOS transistor 326—compared to PMOS transistor 216 and NMOS transistor 220 in FIG. 2—threshold voltages Vt are increased and static leakage currents are reduced. This reverse body biasing lowers the capability of inverter 370 to switch fast.
Example 350 in FIG. 3B includes inverter 370 and other logic gates 380. Supply voltage sources 360-364 coupled to GND rail 358 provide a supply voltage for VDD rail 356. First body-bias voltage source 362 reduces first body-bias voltage VBP for N-well body-bias rail 352, and second body-bias voltage source 364 reduces second body-bias voltage VBN for bulk body-bias rail 354. Inverter 370 includes PMOS transistor 372 with a source 373 coupled to VDD rail 356 and body terminal 374 coupled to N-well body-bias rail 352. It further includes NMOS transistor 376 with a source 377 coupled to GND rail 358 and body terminal 378 coupled to bulk body-bias rail 354. Similarly, other logic gates 380 include PMOS transistors with sources coupled to VDD rail 356 and body terminals coupled to N-well body-bias rail 352, and NMOS transistors with sources coupled to GND rail 358 and body terminals coupled to bulk body-bias rail 354. First body-bias voltage VBP is lower than VDD, and second body-bias voltage VBN is higher than GND. As a result of lower source-to-bulk voltage VBS for PMOS transistor 372 and NMOS transistor 376—compared to PMOS transistor 216 and NMOS transistor 220 in FIG. 2—threshold voltages Vt are reduced and static leakage currents are increased. This forward body biasing increases the capability of inverter 370 to switch fast.
However, the solutions in FIGS. 3A-B still have disadvantages. The addition of first and second body-bias voltage sources increases complexity and cost. If batteries are used, as drawn, this solution may add the cost of the two additional batteries and at least two extra pins on an IC package. If they include voltage regulators or charge pumps, this solution may decrease efficiency because of static and dynamic power consumption by the regulators or charge pumps. Another disadvantage is that designers may have to observe a greater minimum channel length (gate length) for devices that use reverse body biasing.
The present invention, as presented in this specification, aims to address these and other problems in ultra-low-power logic circuits.
Reference to any prior art in the specification is not, and should not be taken as, an acknowledgment or any form of suggestion that this prior art forms part of the common general knowledge in the USA, Australia, or any other jurisdiction or that this prior art could reasonably be expected to be ascertained, understood and regarded as relevant by a person skilled in the art.